`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:24:09 10/21/2012 
// Design Name: 
// Module Name:    vga_sync 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module vga_sync(general_clk_i, general_rst_i,
				    hsync_o , vsync_o , video_on_o, p_tick_o, pixel_x_o, pixel_y_o);

///////PARAMETROS LOCALES ////////////////////////////////////////////////////////	 
localparam HD = 640; // HorizontalDisplay
localparam HF = 48 ; // HFrontBorder
localparam HB = 16 ; // HorizontalBackBorder
localparam HR = 96 ; // HRetrace

localparam VD = 400; // VerticalDisplay
localparam VF = 10; // VerticalFront
localparam VB = 29; // VerticalBack
localparam VR = 2; // VerticalRetrace

///////////////////////////////////////////////////////////////////////////////////


////////////////////////////////PUERTOS DE ENTRADA Y SALIDA////////////////////////
input general_clk_i;
input general_rst_i;
output hsync_o;
output vsync_o;
output video_on_o;
output p_tick_o;
output [9:0] pixel_x_o;
output [9:0] pixel_y_o;
/////////////////////////////////////////////////////////////////////////////////////

///////////////////////////////PROGRAMA DE CONTADORES///////////////////////////////

// mod_2 counter
reg mod2_reg;
wire mod2_next;
//sync counters
reg [9:0] h_count_reg, h_count_next;
reg [9:0] v_count_reg , v_count_next ;
// outpuit buffer
reg v_sync_reg , h_sync_reg ;
wire v_sync_next , h_sync_next ;
// status signal
wire h_end , v_end , pixel_tick;

// body
// registers
always @ (posedge general_clk_i , posedge general_rst_i)
	if (general_rst_i)
		begin
			mod2_reg <= 1'b0;
			v_count_reg <=0;
			h_count_reg <=0;
			v_sync_reg <= 1'b0;
			h_sync_reg <= 1'b0;
		end
	else
		begin
			mod2_reg <= mod2_next ;
			v_count_reg <= v_count_next;
			h_count_reg <= h_count_next;
			v_sync_reg <= v_sync_next ;
			h_sync_reg <= h_sync_next ;
		end
		
// mod-2 circuit to generate 25 MHz enable tick
assign mod2_next = !mod2_reg;
assign pixel_tick = mod2_reg;

// status signals
// end of horizontal counter (799)
assign h_end = (h_count_reg ==(HD+HF+HB+HR-1));
// end of vertical counter (524)
assign v_end = (v_count_reg == (VD+VF+VB+VR-1));


// next-state logic of mod-800 horizontal sync counter
always @*
	if (pixel_tick) 
		if (h_end)
			h_count_next = 0;
		else
			h_count_next = h_count_reg + 1;
	else
		h_count_next = h_count_reg;

// next-state logic of mod-525 vertical sync counter
always @*
	if (pixel_tick & h_end) 
		if (v_end)
			v_count_next = 0;
		else
			v_count_next = v_count_reg + 1;
	else
		v_count_next = v_count_reg;
		

// horizontal and vertical sync, buffered to avoid glitch
// h_svnc_next asserted between 656 and 751
assign h_sync_next = !(h_count_reg>=(HD+HB) && h_count_reg<=(HD+HB+HR-1));
// vh-sync-next asserted between 490 and 491
assign v_sync_next = !(v_count_reg>=(VD+VF) && v_count_reg<=(VD+VF+VR-1));


// video on/off
assign video_on_o = (h_count_reg<HD) && (v_count_reg<VD);
// output
assign hsync_o = h_sync_reg;
assign vsync_o = v_sync_reg;
assign pixel_x_o = h_count_reg;
assign pixel_y_o = v_count_reg;
assign p_tick_o = pixel_tick;


endmodule